1. Field of the Invention
This invention relates to memory circuits.
2. Description of the Prior Art
It is known to use a cache memory to improve the performance of a central processing unit (CPU) in a data processing system. A cache memory is a relatively small, high speed random access memory (RAM) which is used to store data which are frequently required by the CPU. Typically, the cache memory is directly accessed by the CPU (rather than via, for example, an external memory management unit (MMU)) and is situated physically close to the CPU in order to reduce the signal propagation time between the CPU and the cache memory. These features mean that data can be stored in or retrieved from the cache memory very quickly.
Since the cache memory stores only a small subset of the data being handled by the data processing system, it is necessary that the CPU knows whether to retrieve a particular data item from the cache memory or from a (slower) system memory. Accordingly, one previously proposed design of a cache memory comprises a tag memory and an associated data memory. The tag memory is used to store system addresses relating to items of data currently held in the data memory. When the CPU requires access to a data item, a system address associated with that data item is compared with the addresses held in the tag memory. If the address of the current data item matches an address held in the tag memory then the CPU can access that data item in the data memory.
FIG. 1 of the accompanying drawings is a schematic diagram of a previously proposed tag memory, which typically forms part of an integrated circuit. In many cases, the tag memory and associated data memory are implemented with the CPU in a common integrated circuit.
In FIG. 1, an array of memory cells 10 is arranged to provide storage of n data words, each having m bits. Each data word represents a system address of a data item stored in an associated data memory, and is compared with a test address 15 supplied by the CPU. The memory cells and associated circuitry for storing and retrieving one of the n data words are shown in more detail and are indicated as 20.
Each memory cell has two complementary output bitlines, referred to as `bit` and `nbit` (not bit), which ape connected to respective non-inverting and inverting inputs of a corresponding differential sense amplifier 30. Before a read operation is initiated, both bitlines are in a pre-charged (high) state. As the read operation takes place, either the `bit` or the `nbit` bitline is pulled low. The sense amplifier is used to increase the speed of reading data from the memory, by sensing which of the bitlines is being pulled low and quickly generating a binary output in response to that detection.
The outputs of the sense amplifiers 30 therefore represents the m-bit word stored in the corresponding m memory cells 10, and are supplied to respective first inputs of m two-input exclusive NOR (EX-NOR) gates 40. The second input of each EX-NOR gate is connected to a respective bit of the test address 15. The truth table for the exclusive NOR operation is as follows:
______________________________________ Sense amplifier test address EX-NOR output bit output ______________________________________ 0 0 1 0 1 0 1 0 0 1 1 1 ______________________________________
The above truth table shows that the output of each EX-NOR gate is 1 (true) only if the respective bit of the test address 15 is equal to the output of the respective sense amplifier 30.
The outputs of all of the EX-NOR gates 40 are combined by an m-input AND gate 50 to generate a `match` output 60. The match output 60 is equal to 1 (true) only if all of the inputs of the m-input AND gate are also equal to 1 (true). Accordingly, for each m-bit word, the respective match output 60 indicates whether the test address 15 is equal to the address stored as that m-bit word in the tag memory. The match output is then used to control access to the data memory.
Since the aim of a cache memory is to provide the CPU with a very fast access memory, it is important that the access time of the cache memory (and in particular the tag memory) is as low as possible. However, in previously proposed tag memories employing exclusive NOR gates, the exclusive NOR gates can contribute significantly to the total access time of the tag memory. For example, using current technology a typical access time for a tag memory of the type shown in FIG. 1 is about 10 nanoseconds (nS), of which about 2 nS represents the delay imposed by the exclusive NOR gates 40.
In addition, the exclusive NOR function is an awkward function to implement as part of an integrated circuit tag memory. In particular, an exclusive NOR gate generally requires either two gate delays or alternatively both true and complement outputs from a single sense amplifier.
It is also a constant aim in the field of integrated circuit design to reduce the area of an integrated circuit substrate which is required to implement the functions of the integrated circuit.